mcelog Cache Error, how to Disable L3 Cache on Intel i7 CPU – CentOS

Intel has not publicly disclosed how to only disable the L3 cache on most processors, including the Core i7-7567U. Disabling the MTRRs does effectively disable all of the three levels of caches on your processor because all accesses become of type UC (meaning uncacheable), with one possible exception discussed below.

The /proc/mtrr file only list the enabled variable-range MTRRs. However, it doesn’t show you all of the MTRRs. Any other variable-range MTRRs are disabled and you don’t have to worry about them. The fixed-rage MTRRs are still enabled though. These specify memory types of fixed ranges in the bottom 1 MB of the physical address space. Disabling all of the MTRRs listed by /proc/mtrr won’t disable or affect the fixed-range MTRRs. It’s typical for some of the fixed ranges to have cacheable memory types.

According to the relevant memory type resolution rules, a physical memory address not contained in the range of any enabled MTRR has the memory type specified in the lowest 8 bits of the IA32_MTRR_DEF_TYPE MSR register. This type is UC on most or all x86 production systems. You can determine the default type by executing sudo rdmsr -a 0x2ff and checking the lowest 8 bits of the output for each logical core. Note that the MTRRs are actually per physical core, but rdmsr offers no switch to only run one one of the logical cores per physical core.

If you want to disable all MTRRs, the best way is to set bit 11 to zero by executing wrmsr -a 0x2ff 15 0x400, which forces the entire physical address space to be UC. You don’t need to change anything in /proc/mtrr and it’s better to just keep it as is. The -a option is important here because you usually want memory types to not be dependent on which core the code happens to be running on.

There are still a couple of issues with this simple approach. Modern processors include additional MTRRs specific for memory ranges used in system management mode (SMM). These MTRRs can only be modified in SMM. When enabled, any accesses outside of SMM to the memory ranges configured in its MTRRs are ignored. On my system, the memory type specified for the SMM range is WB, so it’s cacheable.

[Temporary notice: Thinking more about it, I’m not sure whether IA32_MTRR_DEF_TYPE[11] controls also the SMM range registers. I’ll have to check with Intel. If it doesn’t, then on processors that support SMM MTRRs, which include yours, the only way to disable caching entirely is by setting CR0.CD to 1. If it does, then no problem.]

Another issue is that I don’t think wrmsr -a 0x2ff 15 0x400 adheres to the recommended procedure for changing MTRRs consistently on all cores of the system, so I would only try it for experimental purposes. On production systems, you may have to write a kernel module to do it properly as described in the manuals.

I don’t think it’s required to writeback and invalidate the caches before disabling the MTRRs because UC accesses are looked up in the caches as well. But I’m unable to find a statement from the Intel or AMD manuals to confirm this at this time.